Since the development of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the area occupied by the integrated components is essentially on the surface of the semiconductor wafer. The increased density and corresponding decrease in area of the integrated circuit has generally given designers more freedom to package the integrated circuit dies. Various techniques have allowed dies to be stacked in different configurations. One configuration is the stacking of dies, such as in a three-dimensional (3D) package. Another is the stacking of one or more dies on an interposer, such as in a two and a half-dimensional (2.5D) package.
In the manufacturing process, various components of a package are routinely tested. In a 2.5D or 3D structure, different dies commonly are tested before stacking. The testing can be expensive and time consuming. High pin counts on the different dies can make testing using probe cards difficult.